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19-2525; Rev 0; 7/02
16-Bit, +5V, 200ksps ADC with 10A Shutdown
General Description
The MAX1162 low-power, 16-bit analog-to-digital converter (ADC) features a successive-approximation ADC, automatic power-down, fast 1.1s wakeup, and a highspeed SPITM/QSPITM/MICROWIRETM-compatible interface. The MAX1162 operates with a single +5V analog supply and features a separate digital supply, allowing direct interfacing with +2.7V to +5.25V digital logic. At the maximum sampling rate of 200ksps, the MAX1162 consumes only 2.5mA. Power consumption is only 12.5mW (AVDD = DVDD = +5V) at a 200ksps (max) sampling rate. AutoShutdownTM reduces supply current to 130A at 10ksps and to less than 10A at reduced sampling rates. Excellent dynamic performance and low power, combined with ease of use and small package size (10-pin MAX and 10-pin DFN) make the MAX1162 ideal for battery-powered and data-acquisition applications or for other circuits with demanding power consumption and space requirements. o +5V Single-Supply Operation o Adjustable Logic Level (+2.7V to +5.25V) o Input Voltage Range: 0 to VREF o Internal Track/Hold, 4MHz Input Bandwidth o SPI/QSPI/MICROWIRE-Compatible Serial Interface o Small 10-Pin MAX or 10-Pin DFN Package o Low Power 2.5mA at 200ksps 130A at 10ksps 0.1A in Power-Down Mode
Features
o 16-Bit Resolution, No Missing Codes
MAX1162
Ordering Information
PART MAX1162ACUB TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 10 MAX 10 DFN 10 MAX 10 DFN 10 MAX 10 DFN 10 MAX 10 DFN 10 MAX 10 DFN 10 MAX 10 DFN INL (LSB) 2 2 2 2 4 4 2 2 2 2 4 4
Applications
Motor Control Industrial Process Control Industrial I/O Modules Data-Acquisition Systems Thermocouple Measurements Accelerometer Measurements Portable- and Battery-Powered Equipment
MAX1162AC_B* MAX1162BCUB MAX1162BC_B* MAX1162CCUB MAX1162CC_B* MAX1162AEUB MAX1162AE_B* MAX1162BEUB MAX1162BE_B* MAX1162CEUB MAX1162CE_B*
*Future product--contact factory for DFN package availability.
Pin Configuration
Functional Diagram appears at end of data sheet. TOP VIEW
REF 1 AVDD AGND CS 2 3 4 5 10 AIN 9 AGND DVDD DGND DOUT
MAX1162
8 7 6
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SCLK
MAX/DFN
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AIN, REF to AGND ...................................-0.3V to (AVDD + 0.3V) SCLK, CS to DGND ..................................................-0.3V to +6V DOUT to DGND .......................................-0.3V to (DVDD + 0.3V) Maximum Current Into Any Pin ...........................................50mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ..........444mW Operating Temperature Ranges MAX1162_CUB .................................................0C to +70C MAX1162_EUB ..............................................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY (NOTE 1) Resolution MAX1162A Relative Accuracy (Note 2) INL MAX1162B MAX1162C Differential Nonlinearity Transition Noise Offset Error Gain Error Offset Drift Gain Drift Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time Serial Clock Frequency Aperture Delay Aperture Jitter Sample Rate Track/Hold Acquisition Time tCONV fSCLK tAD tAJ fS tACQ fSCLK / 24 1.1 (Note 4) 5 0.1 15 <50 200 240 4.8 s MHz ns ps ksps s SINAD SNR THD SFDR -3dB point SINAD > 86dB 92 103 4 10 (Note 3) 86 87 DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 1) 89.5 90 -90 dB dB dB dB MHz kHz (Note 3) DNL No missing codes over temperature MAX1162C RMS noise 0.65 0.1 0.002 0.4 0.2 1 0.01 MAX1162A MAX1162B -1 16 2 2 4 1 1.75 2 LSBRMS mV %FSR ppm/oC ppm/oC LSB LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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16-Bit, +5V, 200ksps ADC with 10A Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER ANALOG INPUT (AIN) Input Range Input Capacitance EXTERNAL REFERENCE Input Voltage Range Input Current DIGITAL INPUTS (SCLK, CS) Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage Three-State Output Leakage Current Three-State Output Capacitance POWER SUPPLIES Analog Supply Digital Supply AVDD DVDD 200ksps Analog Supply Current IAVDD CS = DGND 100ksps 10ksps 1ksps 200ksps Digital Supply Current IDVDD CS = DGND, DOUT = all zeros 100ksps 10ksps 1ksps 4.75 2.7 2.0 1.0 0.1 0.01 0.6 0.3 0.03 0.003 1.0 mA 5.25 5.25 2.5 mA V V VOH VOL IL COUT ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V ISINK = 10mA, DVDD = +4.75V to +5.25V ISINK = 1.6mA, DVDD = +2.7V to +5.25V CS = DVDD CS = DVDD 0.1 15 DVDD 0.25V 0.7 0.4 10 V V A pF VIH VIL IIN VHYST CIN DVDD = +2.7V to +5.25V DVDD = +2.7V to +5.25V VIN = 0 to DVDD 0.1 0.2 15 0.7 x DVDD 0.3 x DVDD 1 V V A V pF VREF VREF = +4.096V, fSCLK = 4.8MHz IREF VREF = +4.096V, SCLK idle CS = DVDD, SCLK idle 3.8 100 0.01 0.01 A AVDD V VAIN CAIN 0 40 VREF V pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1162
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16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Shutdown Supply Current Power-Supply Rejection Ratio SYMBOL IAVDD + IDVDD PSRR CONDITIONS CS = DVDD, SCLK = idle AVDD = DVDD = +4.75V to +5.25V, full-scale input (Note 5) MIN TYP 0.1 68 MAX 10 UNITS A dB
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Acquisition Time SCLK to DOUT Valid CS Fall to DOUT Enable CS Rise to DOUT Disable CS Pulse Width CS Fall to SCLK Rise Setup CS Rise to SCLK Rise Hold SCLK High Pulse Width SCLK Low Pulse Width SCLK Period SYMBOL tACQ tDO tDV tTR tCSW tCSS tCSH tCH tCL tCP 65 65 208 CDOUT = 50pF CDOUT = 50pF CDOUT = 50pF 50 100 0 CONDITIONS MIN 1.1 50 80 80 TYP MAX UNITS s ns ns ns ns ns ns ns ns ns
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Acquisition Time SCLK to DOUT Valid CS Fall to DOUT Enable CS Rise to DOUT Disable CS Pulse Width CS Fall to SCLK Rise Setup CS Rise to SCLK Rise Hold SCLK High Pulse Width SCLK Low Pulse Width SCLK Period SYMBOL tACQ tDO tDV tTR tCSW tCSS tCSH tCH tCL tCP 65 65 208 CDOUT = 50pF CDOUT = 50pF CDOUT = 50pF 50 100 0 CONDITIONS MIN 1.1 100 100 80 TYP MAX UNITS s ns ns ns ns ns ns ns ns ns
Note 1: AVDD = DVDD = +5V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Offset and reference errors nulled. Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 5: Defined as the change in positive full scale caused by a 5% variation in the nominal supply voltage. 4 _______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
Typical Operating Characteristics
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7F, VREF = +4.096V, TA = +25C, unless otherwise noted.)
MAX1162 FFT
MAX1162 toc02 MAX1162 toc03
INL vs. OUTPUT CODE
MAX1162 toc01
DNL vs. OUTPUT CODE
2.0 1.5 1.0 DNL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 MAGNITUDE (dB) 0 -20 -40 -60 -80 -100 -120 -140 0 13107 26214 39322 52429 65536 0 OUTPUT CODE
2.0 1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 13107 26214 39322 52429
65536
OUTPUT CODE
10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz)
SINAD vs. FREQUENCY
MAX1162 toc04
SFDR vs. FREQUENCY
120 110 100 90 SFDR (dB) 80 70 60 50 40 30 20 10 0
MAX1162 toc05
THD vs. FREQUENCY
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
MAX1162 toc06
100 90 80 70 SINAD (dB) 60 50 40 30 20 10 0 0.1 1 10
0
100
0.1
1
10
THD (dB)
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
SUPPLY CURRENT vs. CONVERSION RATE
MAX1162 toc07
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1162 toc08
SUPPLY CURRENT vs. TEMPERATURE
MAX1162 toc09
10
3.5 3.0 SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 0.5
3.5 3.0 SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 0
1 SUPPLY CURRENT (mA)
0.1
0.01
0.001 0.0001 0.01
0 0.1 1 10 100 1000 4.75 4.85 4.95 5.05 5.15 5.25 CONVERSION RATE (kHz) SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
TEMPERATURE (C)
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16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7F, VREF = +4.096V, TA = +25C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1162 toc10
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX1162 toc11
20 18 16 14 ISHDN (nA) 12 10 8 6 4 2 0 4.75 4.85 4.95 5.05 5.15
150 SHUTDOWN SUPPLY CURRENT (nA) 125 100 75 50 25 0
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE
MAX1162 toc12
OFFSET ERROR VS. TEMPERATURE
800 600 OFFSET ERROR (V) 400 200 0 -200 -400 -600 -800 -1000
MAX1162 toc13
1000 800 600 OFFSET ERROR (V) 400 200 0 -200 -400 -600 -800 -1000 4.75 4.85 4.95 5.05 5.15
1000
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
GAIN ERROR vs. ANALOG SUPPLY VOLTAGE
MAX1162 toc14
GAIN ERROR vs. TEMPERATURE
0.015 0.010 GAIN ERROR (%) 0.005 0 -0.005 -0.010 -0.015 -0.020
MAX1162 toc15
0.020 0.015 0.010 GAIN ERROR (%) 0.005 0 -0.005 -0.010 -0.015 -0.020 4.75 4.85 4.95 5.05 5.15
0.020
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
6
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16-Bit, +5V, 200ksps ADC with 10A Shutdown
Pin Description
PIN 1 2 3, 9 4 NAME REF AVDD AGND CS FUNCTION External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7F capacitor. Analog +5V Supply Voltage. Bypass to AGND (pin 3) with a 0.1F capacitor. Analog Ground. Connect pins 3 and 9 together. Place star ground at pin 3. Active-Low Chip-Select Input. Forcing CS high places the MAX1162 in shutdown with a typical current of 0.1A. A high-to-low transition on CS activates normal operating mode and initiates a conversion. Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to 4.8MHz. Serial Data Output. Data changes state on SCLK's falling edge. DOUT is high impedance when CS is high. Digital Ground Digital Supply Voltage. Bypass to DGND with a 0.1F capacitor. Analog Input
MAX1162
5 6 7 8 10
SCLK DOUT DGND DVDD AIN
Detailed Description
The MAX1162 includes an input track-and-hold (T/H) and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 16-bit output. Figure 4 shows the MAX1162 in its simplest configuration. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (Ps). The MAX1162 has two power modes: normal and shutdown. Driving CS high places the MAX1162 in shutdown, reducing the supply current to 0.1A (typ), while pulling CS low places the MAX1162 in normal operating mode. Falling edges on CS initiate conversions that are driven by SCLK. The conversion result is available at DOUT in unipolar serial format. The serial data stream consists of eight zeros followed by the data bits (MSB first). Figure 3 shows the interface timing diagram.
During the acquisition, the analog input (AIN) charges capacitor CDAC. The acquisition interval ends on the falling edge of the sixth clock cycle (Figure 6). At this instant, the T/H switches open. The retained charge on CDAC represents a sample of the input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to zero within the limits of 16-bit resolution. At the end of the conversion, force CS high and then low to reset the input side of the CDAC switches back to AIN, and charge CDAC to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal. Use the following formula to calculate acquisition time: tACQ = 13(RS + RIN) x 35pF where R IN = 800, R S = the input signal's source impedance, and t ACQ is never less than 1.1s. A source impedance less than 1k does not significantly affect the ADC's performance. To improve the input signal bandwidth under AC conditions, drive AIN with a wideband buffer (>4MHz) that can drive the ADC's input capacitance and settle quickly.
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Analog Input
Figure 5 illustrates the input sampling architecture of the ADC. The voltage applied at REF sets the full-scale input voltage. Track-and-Hold (T/H) In track mode, the analog signal is acquired on the internal hold capacitor. In hold mode, the T/H switches open and the capacitive DAC samples the analog input.
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16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
VDD 1mA DOUT 1mA DGND a) VOL TO VOH CLOAD = 50pF DOUT CLOAD = 50pF DGND b) HIGH-Z TO VOL AND VOH TO VOL DOUT 1mA DGND a) VOH TO HIGH-Z CLOAD = 50pF DOUT 1mA
VDD
CLOAD = 50pF DGND b) VOL TO HIGH-Z
Figure 1. Load Circuits for DOUT Enable Time and SCLK to DOUT Delay Time
Figure 2. Load Circuits for DOUT Disable Time
CS tCSW tCSS SCLK tCP tCL tCH tCSH
tDV DOUT
tDO
tTR
TIMING NOT TO SCALE.
Figure 3. Detailed Serial Interface Timing
Input Bandwidth The ADC's input tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, use anti-alias filtering. Analog Input Protection Internal protection diodes, which clamp the analog input to AVDD or AGND, allow the input to swing from AGND - 0.3V to AVDD + 0.3V, without damaging the device. If the analog input exceeds 300mV beyond the supplies, limit the input current to 10mA.
AIN VREF 4.7F +5V 0.1F +5V 0.1F
AIN REF AVDD DVDD MAX1162
CS SCLK DOUT
CS SCLK DOUT
AGND DGND
GND
Figure 4. Typical Operating Circuit 8 _______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10A Shutdown
Digital Interface
Initialization after Power-Up and Starting a Conversion
The digital interface consists of two inputs, SCLK and CS, and one output, DOUT. A logic high on CS places the MAX1162 in shutdown (AutoShutdown) and places DOUT in a high-impedance state. A logic low on CS places the MAX1162 in the fully powered mode. To start a conversion, pull CS low. A falling edge on CS initiates an acquisition. SCLK drives the A/D conversion and shifts out the conversion results (MSB first) at DOUT.
AIN CSWITCH 3pF REF TRACK CAPACITIVE DAC ZERO HOLD GND HOLD CDAC 32pF RIN 800 TRACK
MAX1162
AUTO-ZERO RAIL
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs (Figures 6 and 7). Ensure that the duty cycle on SCLK is between 40% and 60% at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure that the minimum high and low times are at least 65ns. Conversions with SCLK rates less than 100kHz can result in reduced accuracy due to leakage. Note: Coupling between SCLK and the analog inputs (AIN and REF) may result in an offset. Variations in frequency, duty cycle, or other aspects of the clock signal's shape result in changing offset. A CS falling edge initiates an acquisition sequence. The analog input is stored in the capacitive DAC, DOUT changes from high impedance to logic low, and the ADC begins to convert after the sixth clock cycle. SCLK drives the conversion process and shifts out the conversion result on DOUT. SCLK begins shifting out the data (MSB first) after the falling edge of the 8th SCLK pulse. Twenty-four falling
Figure 5. Equivalent Input Circuit
clock edges are needed to shift out the eight leading zeros and 16 data bits. Extra clock pulses occurring after the conversion result has been clocked out, and prior to the rising edge of CS, produce trailing zeros at DOUT and have no effect on the converter operation. Force CS high after reading the conversion's LSB to reset the internal registers and place the MAX1162 in shutdown. For maximum throughput, force CS low again to initiate the next conversion immediately after the specified minimum time (tCSW). Note: Forcing CS high in the middle of a conversion immediately aborts the conversion and places the MAX1162 in shutdown.
Output Coding and Transfer Function
CS SCLK DOUT tDV
1 tCSS tCH tACQ tDO tTR 4 tCL 6 8 D15 D14 D13 12 D12 D11 D10 D9 16 D8 D7 D6 D5 20 D4 D3 D2 D1 24 tCSH D0
Figure 6. External Timing Diagram _______________________________________________________________________________________ 9
16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
COMPLETE CONVERSION SEQUENCE CS
DOUT CONVERSION 0 CONVERSION 1
POWERED UP TIMING NOT TO SCALE.
POWERED DOWN
POWERED UP
Figure 7. Shutdown Sequence
The data output from the MAX1162 is binary and Figure 8 depicts the nominal transfer function. Code transitions occur halfway between successive-integer LSB values (VREF = 4.096V and 1LSB = 63V or 4.096V/65536).
OUTPUT CODE FULL-SCALE TRANSITION
11 . . . 111 11 . . . 110 11 . . . 101
Applications Information
External Reference
The MAX1162 requires an external reference with a +3.8V and AVDD voltage range. Connect the external reference directly to REF. Bypass REF to AGND (pin 3) with a 4.7F capacitor. When not using a low-ESR bypass capacitor, use a 0.1F ceramic capacitor in parallel with the 4.7F capacitor. Noise on the reference degrades conversion accuracy. The input impedance at REF is 40k for DC currents. During a conversion the external reference at REF must deliver 100A of DC load current and have an output impedance of 10 or less. For optimal performance, buffer the reference through an op amp and bypass the REF input. Consider the MAX1162's equivalent input noise (38V RMS ) when choosing a reference.
00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 2 3 INPUT VOLTAGE (LSB)
FS = VREF V 1LSB = REF 65536
FS FS - 3/2LSB
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF, Zero Scale (ZS) = GND
Input Buffer
Most applications require an input buffer amplifier to achieve 16-bit accuracy. If the input signal is multiplexed, switch the input channel immediately after acquisition, rather than near the end of or after a conversion (Figure 9). This allows the maximum time for the input buffer amplifier to respond to a large step change in the input signal. The input amplifier must have a slew rate of at least 2V/s to complete the required output voltage change before the beginning of the acquisition time. At the beginning of the acquisition, the internal sampling capacitor array connects to AIN (the amplifier output),
10
causing some output disturbance. Ensure that the sampled voltage has settled before the end of the acquisition time. Digital Noise Digital noise can couple to AIN and REF. The conversion clock (SCLK) and other digital signals active during input acquisition contribute noise to the conversion result. Noise signals synchronous with the sampling interval result in an effective input offset. Asynchronous signals produce random noise on the input, whose high-frequency components can be aliased into the frequency band of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the
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16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
IN1 IN2
A0
A1
4-TO-1 MUX AIN OUT CS
MAX1162
IN3 IN4
CLK CONVERSION CS ACQUISITION
A0
A1
TIMING NOT TO SCALE.
CHANGE MUX INPUT HERE
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
noise signal) at the inputs. This requires bypassing AIN to AGND, or buffering the input with an amplifier that has a small-signal bandwidth of several MHz, or preferably both. AIN has 4MHz (typ) of bandwidth. Distortion Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the MAX1162's total harmonic distortion (THD = -102dB at 1kHz) at frequencies of interest. If the chosen amplifier has insufficient common-mode rejection, which results in degraded THD performance, use the inverting configuration (positive input grounded) to eliminate errors from this source. Low temperature-coefficient, gain-setting resistors reduce linearity errors caused by resistance changes due to selfheating. To reduce linearity errors due to finite amplifier gain, use amplifier circuits with sufficient loop gain at the frequencies of interest.
DC Accuracy To improve DC accuracy, choose a buffer with an offset much less than the MAX1162's offset (1mV (max) for +5V supply), or whose offset can be trimmed while maintaining stability over the required temperature range.
Serial Interfaces
The MAX1162's interface is fully compatible with SPI, QSPI, and MICROWIRE standard serial interfaces. If a serial interface is available, establish the CPU's serial interface as master, so that the CPU generates the serial clock for the MAX1162. Select a clock frequency between 100kHz and 4.8MHz: 1) Use a general-purpose I/O line on the CPU to pull CS low. 2) Activate SCLK for a minimum of 24 clock cycles. The serial data stream of eight leading zeros followed by the MSB of the conversion result begins at the falling edge of CS. DOUT transitions on SCLK's falling edge and the output is available in MSB-first
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16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the P on SCLK's rising edge. 3) Pull CS high at or after the 24th falling clock edge. If CS remains low, trailing zeros are clocked out after the least significant bit (D0 = LSB). 4) With CS high, wait at least 50ns (tCSW) before starting a new conversion by pulling CS low. A conversion can be aborted by pulling CS high before the conversion ends. Wait at least 50ns before starting a new conversion. Data can be output in three 8-bit sequences or continuously. The bytes contain the results of the conversion padded with eight leading zeros before the MSB. If the serial clock has not been idled after the LSB (D0) and CS has been kept low, DOUT sends trailing zeros.
SPI and MICROWIRE Interfaces
When using the SPI (Figure 10a) or MICROWIRE (Figure 10b) interfaces, set CPOL = 0 and CPHA = 0. Conversion begins with a falling edge on CS (Figure 10c). Three consecutive 8-bit readings are necessary to obtain the entire 16-bit result from the ADC. DOUT data transitions on the serial clock's falling edge. The first 8-bit data stream contains all leading zeros. The second 8-bit data stream contains the MSB through D8. The third 8-bit data stream contains D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and CPHA = 0, the MAX1162 supports a maximum fSCLK of 4.8MHz. Figure 11a shows the MAX1162 connected to a QSPI master and Figure 11b shows the associated interface timing.
I/O SCK MISO SPI VDD
CS SCLK DOUT MICROWIRE
I/O SK SI
CS SCLK DOUT
MAX1162
SS
MAX1162
Figure 10a. SPI Connections
1ST BYTE READ SCLK CS 1 4 6 8
Figure 10b. MICROWIRE Connections
2ND BYTE READ 12 16
DOUT*
0
0
0
0
0
0
0
0
D15 MSB
D14
D13
D12
D11
D10
D9
D8
D7
*WHEN CS IS HIGH, DOUT = HIGH-Z 3RD BYTE READ 20 24
HIGH-Z TIMING NOT TO SCALE. D7 D6 D5 D4 D3 D2 D1 D0 LSB
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0) 12 ______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
CS SCK QSPI MISO VDD
CS SCLK DOUT
MAX1162
SS
Figure 11a. QSPI Connections
SCLK CS DOUT*
1
4
6
8
12
16
20
24
END OF ACQUISITION
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
LSB
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
VDD
VDD
PIC16 with SSP Module and PIC17 Interface
The MAX1162 is compatible with a PIC16/PIC17 microcontroller (C) using the synchronous serial-port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 12a. Configure the PIC16/PIC17 as system master, by initializing its synchronous serial-port control register (SSPCON) and synchronous serial-port status register (SSPSTAT) to the bit patterns shown in Tables 1 and 2. In SPI mode, the PIC16/PIC17 C allows 8 bits of data to be synchronously transmitted and received simulta-
SCLK DOUT CS
SCK SDI I/O PIC16/17
MAX1162
GND
Figure 12a. SPI Interface Connection for a PIC16/PIC17
Table 1. Detailed SSPCON Register Contents
CONTROL BIT WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX1162 SETTINGS X X 1 0 0 0 0 1 Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16. SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write Collision Detection Bit Receive Overflow Detect Bit Synchronous Serial-Port Enable Bit: 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins. Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
X = Don't care. ______________________________________________________________________________________ 13
16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
Table 2. Detailed SSPSTAT Register Contents
CONTROL BIT SMP CKE D/A P S R/W UA BF BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX1162 SETTINGS 0 1 X X X X X X SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT) SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer Full Status Bit
X = Don't care.
1ST BYTE READ SCLK CS
2ND BYTE READ 12 16
DOUT*
0
0
0
0
0
0
0
0
D15 MSB
D14
D13
D12
D11
D10
D9
D8
D7
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ 20 24
HIGH-Z TIMING NOT TO SCALE. D7 D6 D5 D4 D3 D2 D1 D0 LSB
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
neously. Three consecutive 8-bit readings (Figure 12b) are necessary to obtain the entire 16-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the C on SCLK's rising edge. The first 8-bit data stream contains all zeros. The second 8-bit data stream contains the MSB through D8. The third 8-bit data stream contains bits D7 through D0.
tion, once offset and gain errors have been nulled. The static linearity parameters for the MAX1162 are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of 1LSB guarantees no missing codes and a monotonic transfer function.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-fit straight line fit or a line drawn between the endpoints of the transfer func14
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in the time between samples. Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when the actual sample is taken.
______________________________________________________________________________________
16-Bit, +5V, 200ksps ADC with 10A Shutdown
ENOB = (SINAD - 1.76) / 6.02 Figure 13 shows the effective number of bits as a function of the MAX1162's input frequency.
MAX1162
ENOB vs. INPUT FREQUENCY
16 14 12 EFFECTIVE BITS 10 8 6 4 2 0 0.1 1 10 100 INPUT FREQUENCY (kHz)
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V4 2 + V52 THD = 20 x log V1
where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Figure 13. Effective Number of Bits vs. Input Frequency
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADCs resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest frequency component.
Supplies, Layout, Grounding, and Bypassing
Use PC boards with separate analog and digital ground planes. Do not use wire-wrap boards. Connect the two ground planes together at the MAX1162 (pin 3). Isolate the digital supply from the analog with a lowvalue resistor (10) or ferrite bead when the analog and digital supplies come from the same source (Figure 14).
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals, excluding the DC offset. SignalRMS SINAD(dB) = 20 x log (Noise + Distortion) RMS
AIN VREF 4.7F +5V 10 0.1F 0.1F DVDD AGND DGND AVDD MAX1162 AIN REF CS SCLK DOUT CS SCLK DOUT
Effective Number of Bits
Effective number of bits (ENOB) indicate the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows:
GND
Figure 14. Powering AVDD and DVDD from a Single Supply
______________________________________________________________________________________
15
16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
Constraints on sequencing the power supplies and inputs are as follows: * Apply AGND before DGND. * Apply AIN and REF after AVDD and AGND are present. * DVDD is independent of the supply sequencing. Ensure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. A 5mA current flowing through a PC board ground trace impedance of only 0.05 creates an error voltage of about 250V, 4LSB error with a +4V fullscale system. The board layout should ensure that digital and analog signal lines are kept separate. Do not run analog and digital (especially the SCLK and DOUT) lines parallel to one another. If one must cross another, do so at right angles. The ADCs high-speed comparator is sensitive to highfrequency noise on the AVDD power supply. Bypass an excessively noisy supply to the analog ground plane with a 0.1F capacitor in parallel with a 1F to 10F low-ESR capacitor. Keep capacitor leads short for best supply-noise rejection.
Functional Diagram
AVDD DVDD
REF AIN AGND TRACK AND HOLD 16-BIT SAR ADC OUTPUT BUFFER DOUT
SCLK
CONTROL
CS MAX1162
DGND
Chip Information
TRANSISTOR COUNT: 12,100 PROCESS: BiCMOS
16
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16-Bit, +5V, 200ksps ADC with 10A Shutdown MAX1162
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
1 1
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 0.120 E1 0.116 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b D1 A1
E2 c E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
Note: Contact factory for DFN package outline.
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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